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name
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4
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2024-02-10 07:35:04
expired found date
2025-04-30 23:50:28
created at
2024-06-18 14:11:33
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2025-04-30 23:50:28
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27
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title
description
image
site name
author
updated
2026-02-27 07:12:04
raw text
Sadegh Dalvandi Sadegh Dalvandi Home Publications Photos About I am a formal verification engineer and researcher. My main research interest is the application of formal methods in software and hardware. I am particularly interested in tools and methods for developing verified programs and program verification. I have worked on various subjects including verified code generation, weak memory, transactional memory, and concurrency verification. Currently, I am working at Axiomise , a formal verification consulting company. I am also a visiting researcher at the University of Surrey. From 2019 to 2022, I was a research fellow at the University of Surrey working with Dr Brijesh Dongol . Prior to joining Surrey University, I was a research fellow at the University of Southampton working with Professor Michael Butler on the PRiME project. I did my PhD in Computer Science (2017) under Michael 's supervision at the School of Electronics and Computer Science, Universi...
redirect type
0 (-)
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0 (no issues)
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1 (English)
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1
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text cyrillic
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text characters
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2026-02-27 07:12:04
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